First phase enabled AMD Turin support in coreboot: created turin_poc SoC tree, integrated OpenSIL drivers, and compiled the port for the Gigabyte MZ33-AR1 board.
Prepared and hooked up Turin PSP firmware blobs by adding AMD’s firmwares as submodules, patching amdfwtool, and improving PSPTool to extract APCB/APOB data.
Built a minimal mainboard skeleton with bootblock, devicetree, and recovery blobs, and devised a no-PSP workaround to flash and see serial output on hardware.
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