Moore’s Law of doubling transistor density every two years is hitting both physical and economic limits.
The cost to build leading-edge chip factories has risen from a few billion dollars to over $100 billion, reducing the number of viable manufacturers.
‘Nanometer’ labels on chip nodes are now marketing terms and no longer reflect actual transistor dimensions.
Extreme Ultraviolet (EUV) lithography and photoresist chemistry face fundamental wavelength and material limits around 5–10 nm.
Transistor designs evolved from planar to FinFET to GAAFET and CFET have grown increasingly complex and costly.
Dennard scaling ended around 2006, causing clock speeds to stagnate and power density challenges to rise.
High photomask costs and stringent defect rates make small-scale chip production economically unfeasible for many players.
Future progress may require simpler, low-cost manufacturing, defect-tolerant designs, and rethinking chip lifecycles.
Get notified when new stories are published for "🇺🇸 Hacker News English"